qualcommax: ipq50xx: correct assigned cmn pll clock rate

qualcommax: ipq50xx: correct assigned cmn pll clock rate

In IPQ5018, the reference clock to the CMN PLL block from the on-board
Wi-Fi has its divider set to 2. This divider wasn't taken into
consideration when calculating the CMN PLL clock rate which meant the
resulting clock rate was doubled.

With the reference clock divider being accounted for in the driver,
correct the assigned clock rate to 4.8GHz.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/21453
Signed-off-by: Robert Marko <robimarko@gmail.com>